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data processor S5A1903X01 1 introduction the S5A1903X01 implements the voice intelligibility processor (vip). the vip is a signal processing algorithm designed to increase the intelligibility of human speech in a high ambient noise environment. unlike noise cancellation or adaptive speech filtering systems, vip operates on the speech signal only and is totally independent of the noise. this approach makes speech clearer and easier to understand regardless of the characteristics of the noise source, and eliminates the need for processing of the noise signal. in addition to vip, the S5A1903X01 includes voice equalizer. the equalizer is composed of four different frequency bands, and each band is controlled between +12db and -12db. thus, it can be used to compensate of speaker characteristics. the figure 1 shows how the S5A1903X01 interfaces to vocoder and codec in cellular phone. main features ? ip mode ? equalizer mode ? 16-bit fixed point dsp core ? two internal 256-word data ram ? 2k-word internal program rom ? wide range of system clock : 8 - 40 mhz ? pcm input/ output interface ? i 2 c host interface ? low power consumption less than 4ma in working mode 10ua in sleep mode ? packages: 32-lqfp/ 32-bcc ? 3v single power supply ordering information applications ? cellular phone ? wireless and traditional telephone device package temperature range S5A1903X01-e0r0 32 lqfp 0 c - 70 c 32-lqfp
S5A1903X01 data processor 2 block diagram system block diagram vocoder resb scl sda din fs mclk vip dout voice codec ckin
data processor S5A1903X01 3 chip block diagram msm vocoder i 2 c i/f vip ssp1611 sram 256 codec digital i/f p.rom 2k sram 256 note: not scaled
S5A1903X01 data processor 4 functional block diagram din pcm input i/f pcm output i/f dout voice intelligibility proces bpf (center: 300hz) bpf (center: 600hz) bpf (center: 1.2khz) hpf (cutoff: 2.4khz) +
data processor S5A1903X01 5 pin assignments 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 17 16 15 14 13 12 11 24 23 22 21 20 19 18 S5A1903X01 32bcc (top view) vdd4 todr gpo3 gpo2 dout gnd4 gpo1 scl sda gnd2 ckin vdd2 mclk din gpo0 vdd1 gpi0 gpi1 gpi2 gpi3 gnd1 resb fs tclkdr tidr tshftdr gnd3 tupddr tseldr1 tsekdr0 vdd3 sas
S5A1903X01 data processor 6 pin description related block pin name pin no. i/o description resb 8 i reset: active low hiu sda 15 i/o i 2 c serial data scl 16 i i 2 c serial clock sas 17 i i 2 c address selection din 10 i 16 bit pcm serial data in ciu dout 30 o 16 bit pcm serial data out fs 9 i pcm data frame sync. mclk 11 i pcm data bit clock system ckin 13 i system clock (9.84mhz) gpi0 3 i test pin0 (host int. indicator) gpi1 4 i test pin1(0:no fade, 1:fade) gpi2 5 i test pin2 (0:ram test) gpi3 6 i test pin3 (0:codec bypass) tseldr0 19 i test pin for jtag tseldr1 20 i test pin for jtag test tupddr 21 i test pin for jtag tshftdr 23 i test pin for jtag tidr 24 i test pin for jtag tclkdr 25 i test pin for jtag todr 27 o test pin for jtag gpo0 1 o host ack. pin gpo1 32 o host test output gpo2 29 o host test output gpo3 28 o host test output power vdd1, vdd2 vdd3, vdd4 2, 12, 18, 26 p digital power (+3.0v) ground gnd1, gnd2 gnd3, gnd4 7, 14, 22, 31 g digital gnd
data processor S5A1903X01 7 dsp port assignment for i/f with peripherals hardware specification codec interface unit (ciu) ? - time diagram important!: during fs (frame sync. clock) high, the falling edge of mclk (pcm bit clock) should exist one time. i/f read/ write port interrupt hiu read ext1 int1 write ext1 ciu read ext0 int0 write ext0 fs 1 2 3 4 5 6 15 16 15 16 7 1 2 3 4 5 6 7 ~ ~ ~ ~ ~ ~ mclk din dout
S5A1903X01 data processor 8 host interface unit (hiu) ? i 2 c bus interface the vip can be controlled by a microcontroller via the 2-line i2c bus, sda (serial data line) and scl (serial clock line). both lines must be connected to a positive supply via pull-up resistor. data transfer may be initiated only when the bus is not busy. when the bus is free, both lines are high. the data on the sda line must be stable during the high period of clock, scl. when the scl is low, the sda can change. every byte transferred through the sda line must contain 8 bits including programmable slave address and read/write direction control bit. each byte must be followed by acknowledge bit which is sent back to the microcontroller by the vip by pulling down the sda line. the msb is transferred first. ? i 2 c bus interface start and stop condition the start condition is high to low transition of the sda line while the scl is high. the stop condition is low to high transition of the sda line while scl is high. sda scl sda scl data valid change of data allowed s p start condition stop condition
data processor S5A1903X01 9 ? i 2 c bus interface acknowledge the acknowledge related clock pulse is generated by a microcontroller. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. the slave-transmitter generates negative acknowledge when read operation processes. the negative acknowl- edge is generated by a master (microcontroller). scl sda s 1 0 0 0 0 a0 a w a a p 0 s 1 0 0 0 0 0 0 0 p lsb msb data lsb msb function address lsb msb chip address i 2 c bus interface format-write operation scl sda s 1 0 0 0 0 a0 a r a n/ a p 0 s 1 0 0 0 0 0 0 1 p lsb msb data lsb msb function address lsb msb chip address i 2 c bus interface format-read operation
S5A1903X01 data processor 10 command summary ic address command data description 80h 01h - bypass (default, dsp off) 80h 02h - vip 80h 03h - equalizer 80h 04h - equalizer flat 80h 05h - equalizer mode1 80h 06h - equalizer mode2 80h 07h - equalizer mode3 80h 08h - equalizer mode4 00h vip level 100% 80h 09h 01h vip level 80% 02h vip level 60% bit[7:5] bit[4:0] 000b band1 gain control 80h 0ah 001b 00000h - band2 gain control 010b 11000h band3 gain control 011b band4 gain control 80h 0bh * * h host test mode (return **h). read after ic read address 0x81 bit [7:4] bit [3:0] 0h 0h - ch vip filter1 gain control 80h 0ch ... 0h - ch bit [3:0] = 0h: +12db, bit [3:0] = ch: 0db, 1db step 9h 0h - ch vip filter10 gain control 80h 0dh 00h - ffh noise level selection 80h 01h return current status followed by ic read address 0x81, [7:4] = unused, [3:2] = vip level, [1] = working mode(0:vip, 1:eq), [0] = bypass flag (0: dsp on, 1: dsp off) 80h 01h return band1 tone level status followed by ic read address 0x81 (00h: -12db - 18h: + 12db) 80h 0eh 02h return band2 tone level status followed by ic read address 0x81 80h 03h return band3 tone level status followed by ic read address 0x81 80h 04h return band4 tone level status followed by ic read address 0x81
data processor S5A1903X01 11 description ? bypass mode ? format ? description in bypass mode, din (pcm input data line) is directly connected to dout (pcm output data line) and the dsp is in stop mode. ? vip mode ? format ? description this one byte command selects vip mode. equalizer mode ? format ? description this one byte command selects equalizer mode. default tone levels are dipicted in command code (hex) command name 01 bypass command code (hex) command name 02 vip command code (hex) command name 03 eq
S5A1903X01 data processor 12 figure 1: default tone level (band1: + 4db, band2: 0db, band3: 0db, band4: +1db) ? vip level select ? format ? description when the current mode is the vip, its level can be changed using incoming data byte after the command. the default vip level is 80%. command code (hex) data (hex) command name description 00 100% (max.) 04 01 vip level 80% (mid.) 02 60% (min.) -30 -20 0 10 -10 10 2 10 3
data processor S5A1903X01 13 ? eq mode select ? format ? description although equalizer can control all four bands, it assigns five preset tone level modes. ? eq tone select ? format ? description the equalizer controls four different frequency bands. the gain for each frequency band can be controlled between -12db and +12db. the [7:5] in data byte after the command determines the frequency band to be controlled and [4:0] determines gain level. command code (hex) command name description 05 eq flat all bands are set to 0db 06 eq mode1 band1: +3db, band2: -1db, band3: -1db, band4: +1db 07 eq mode2 band1: +3db, band2: 0db, band3: 0db, band4: +3db 08 eq mode3 band1: +5db, band2: 0db, band3: 0db, band4: 0db 09 eq mode4 band1: +5db, band2: 0db, band3: 0db, band4: +1db command code (hex) data description command name [7:5] 00 band1 select 01 band2 select 10 band3 select 11 band4 select [4:0] 00000 +12db 0a 00001 +11db tone control ?| 01100 0db ?| 10111 -11db 11000 -12db
S5A1903X01 data processor 14 ? vip filter gain selection ? format ? description these commands select the gains of filter outputs in the vip mode. the detailed description of filter structure can be found in "vip specification" published by srs labs. command code (hex) data (hex) description command name 0 150hz filter gain to servo 1 300hz filter gain to servo 2 150hz & 300 hz sum gain 3 600hz filter gain to servo [7:4] 4 1.2khz filter gain to summer 5 1.2khz filter gain to servo 0b 6 2.4khz filter gain to summer vip filter gain control 7 2.4khz filter gain to servo 8 4.8khz filter gain to summer 9 4.8khz filter gain to servo 0 + 12db [3:0] 1 + 11db ..... c 0db
data processor S5A1903X01 15 ? noise level selection ? format ? description when the input from adc has small noise, this noise can incresed in vip or eq mode since the specific frequency levels are increased. to avoid this problem in mute, the input data is tested for 25ms. if the absolute values of input data are less than noise level specified in data and stay for 25ms, then the input is considered as zeros and are processed. default noise level is set to 0x1f. ? current status ? format ? description it returns the contents of the current status register as: status [7:4] = unused status [3:2] = vip level (00: 100%, 01: 80%, 10: 60%) status [1] = working mode (0: vip, 1:eq) status [0] = dsp on/off (0: dsp on, 1: dsp off) ? eq tone level status ? format ? description these commands return the current tone levels in eq mode. returned byte value is between 0x00 (-12db) and 0x18 (+12db). command code (hex) data (hex) description command name 0d 00 - ff assume the value in data as noise level noise level select command code (hex) data (hex) description command name 0e 01 return current status register contents current status command code (hex) data (hex) description command name 02 return current band1 tone level 0e 03 return current band2 tone level current tone level 04 return current band3 tone level status 05 return current band4 tone level
S5A1903X01 data processor 16 memory size and required mips memory size * word = 16 bit mips memory size (word*) data bank 0 256 bank 1 256 vip 800 4band eq 500 program test 400 others 100 total 1860 routines no. of cycles mips remark vip 650 5.2 - 4band eq 400 3.2 working only when vip is off others 80 0.64 - total (vip on) = 650 + 70 + 80 = 800 (6.4 mips)
data processor S5A1903X01 17 8. electrical characteristics (unless otherwise specified, vcc = 2.7v to 3.3v, ta = -30c to 85c ; typical characteristic are specified at vcc = 3.0v, ta = 25c; all signals are referenced to gnd) digital interfaces notes: 1. normal output pin 2. sda ,scl output pin 3. input buffer with pull -up (resb pin) 4. input buffer with pull -down (2, 3, 4, 5, 6, 17, 19, 20, 21, 23, 24, 25 pin) power dissipation (@3.3v) symbol parameter test condition min. typ. max. unit vil input low voltage 0.8 v vih input high voltage 1.9 v i ol = 1ua 0.05 v vol output low voltage i ol = 4ma (see note1) 0.4 v i ol = 8ma (see note 2) i oh = -1ua v dd -0.05 v voh output high voltage i oh = -4ma (see note1) 2.4 v i oh = -8ma (see note2) iil input low current v in = vss -10 10 ua v in = v ss (see note3) -60 -30 -10 ua iih input high current v in = v dd -10 10 ua v in = v dd (see note4) 60 30 10 ua ioz output current in high impedance (tri-state) v out = v ss or v dd -5 5 ua symbol parameter test condition min. typ. max. unit icc0 operation current vip or eq operation mode - 3 4 ma icc1 bypass current bypass operation mode - 100 150 ua icc2 static current no operation (sleep mode) - 10 ua
S5A1903X01 data processor 18 package dimension 32 bcc type 0.15 0.03 c c a b 0.40 + 0.10 0.15 0.03 c c a b 0.50 + 0.10 0.50 + 0.10 pin cd.2 4.20 4.15 0.45 + 0.10 0.50 + 0.10 0.75 + 0.025 5.00 + 0.10 index ???? marking types 4x 0.15 a b 0.60 max / / 0.20 c 0.15 c
data processor S5A1903X01 19 #32 7.00 + 0.20 9.00 + 0.30 7.00 + 0.20 9.00 + 0.30 #1 0.30 + 0.10 0.80 0.10 max (0.70) 0.10 max 0.50 + 0.20 0.05 min 1.40 + 0.10 0-8 170 max 0.127 + 0.10 - 0.05
S5A1903X01 data processor 20 notes

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